Field of the Invention
The present invention relates to an array substrate and more particularly to an array substrate including an oxide semiconductor layer on top of source and drain electrodes and a method of fabricating the array substrate that reduces production processes.
Discussion of the Related Art
Flat panel display devices have a thin profile, light weight and low power consumption. Among these devices, an active matrix type liquid crystal display (LCD) device is widely used for notebook computers, monitors, TV, and so on instead of a cathode ray tube (CRT), because of their high contrast ratio and characteristics adequate to display moving images.
On the other hand, an organic electroluminescent display (OELD) device is also widely used because of their high brightness and low driving voltage, e.g., 5 to 15 V. In addition, because the OELD device is a self-emission type, the OELD device has a high contrast ratio, a thin profile and a fast response time. In addition, both the LCD and OELD devices include an array substrate with a thin film transistor (TFT) as a switching element in each pixel for turning on and off the pixel.
In more detail, FIG. 1 is a cross-sectional view showing one pixel region of a related art array substrate. In FIG. 1, a gate electrode 15 is formed on a substrate 11 and in a switching region “TrA”, where a TFT “Tr” is formed inside a pixel region “P”. A gate line connected to the gate electrode 15 is also formed along a first direction. A gate insulating layer 18 is formed on the gate electrode 15 and the gate line, and a semiconductor layer 28 including an active layer 22 of intrinsic amorphous silicon and an ohmic contact layer 26 of impurity-doped amorphous silicon is formed on the gate insulating layer 18 and in the switching region “TrA”.
Further, a source electrode 36 and a drain electrode 38 are formed on the semiconductor layer 28 and in the switching region “TrA”. As shown, the source electrode 36 is spaced apart from the drain electrode 38, and a data line 33 connected to the source electrode 36 is formed along a second direction. The data line 33 crosses the gate line to define the pixel region “P”. In addition, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, the source electrode 36 and the drain electrode 38 constitute the TFT “Tr”.
Further, a passivation layer 42 including a drain contact hole 45 is formed to cover the TFT “Tr”. A pixel electrode 50 connected to the drain electrode 38 through the drain contact hole 45 is formed on the passivation layer 42. In FIG. 1, first and second patterns 27 and 23, which are respectively formed of the same material as the ohmic contact layer 26 and the active layer 22, are formed under the data line 33.
In the semiconductor layer 28 of the TFT “Tr”, the active layer 22 of intrinsic amorphous silicon has a difference in a thickness. Namely, the active layer 22 has a first thickness “t1” under the ohmic contact layer 26 and a second thickness “t2” at a center. The first thickness “t1” is different from the second thickness “t2”. In addition, the (t1≠t2) Properties of the TFT “Tr” are degraded by the thickness difference in the active layer 22. The thickness difference in the active layer 22 results from a fabricating process.
Recently, the TFT including a single semiconductor layer of an oxide semiconductor material without the ohmic contact layer has been introduced. Because the oxide semiconductor TFT does not need the ohmic contact layer, a dry-etching process for etching the ohmic contact layer is not performed. As a result, the oxide semiconductor layer does not have a thickness difference, and thus the properties of the oxide semiconductor TFT are improved.
In addition, the oxide semiconductor layer has a larger mobility as much as several to several tens times than the amorphous silicon semiconductor layer. Thus, there are advantages in using the oxide semiconductor TFT as a switching or driving element. However, when the oxide semiconductor layer is exposed to an etchant for patterning a metal layer, the oxide semiconductor layer is also patterned because the oxide semiconductor material does not have an etching selectivity to the etchant. The molecular structure of the oxide semiconductor material is also damaged by the etchant. As a result, the properties of the TFT are degraded. In particular, in a bias temperature stress (BTS) test, a threshold voltage is significantly varied such that the TFT significantly affects a display quality of the array substrate.
To resolve these problems, the cross-sectional view of FIG. 2 shows an array substrate including the related art TFT “Tr” having a gate electrode 73, a gate insulating layer 75, an oxide semiconductor layer 77 on a substrate 71, and an etch-stopper 79 of an inorganic insulating material formed on the oxide semiconductor layer 77. Thus, when a metal layer is patterned using an etchant to form source and drain electrodes 81 and 83, the oxide semiconductor layer 77 is not exposed to the etchant due to the etch-stopper 77. The reference numbers “85”, “87” and “89” refer to the passivation layer, the drain contact hole and the pixel electrode, respectively.
However, the array substrate including the oxide semiconductor layer 77 and the etch-stopper 79 requires an additional mask process for the etch-stopper 79. Since the mask process includes coating a photoresist (PR) layer, exposing the PR layer using an exposing mask, developing the exposed PR layer to form a PR pattern, etching a material layer using the PR pattern as an etching mask, and stripping the PR pattern, the mask process includes many disadvantages such as an increase in production costs, a decrease in production yield, and so on.